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| (R) PRELIMINARY February 1998 S IG N DES EW at RN nt e r D FO 2 DE 408 t Ce /tsc N or M M E e e H I P l S up p i l . c o m S ECO ica inters R ch n w w . N OT r Te t o u IL o r w c RS ont a or c 8-INTE -88 1 HIP4084 80V, 0.50A Four Phase Driver Features * Independently Drives 8 N-Channel MOSFETs in Either Four Phase Bridge Configuration or Dual H-Bridge Configuration * 1.25A Peak Turn-Off Current * Bootstrap Supply Max Voltage to 95VDC * Bias Supply Operation from 7V to 15V * User-Programmable Dead Time (0.25s to 4.5s) * Charge-Pump and Bootstrap Maintain Upper Bias Supplies * Drives 1000pF Load with Typical Rise Time of 20ns and Fall Time of 10ns * EN (Disable) Overrides Input Control * Input Logic Thresholds Compatible with 3V to 15V Logic Levels * Dead Time Disable Capability * Programmable Undervoltage Set Point Description The HIP4084 is a Four Phase Bridge N-Channel MOSFET driver IC. Specifically targeted for PWM and stepper motor control applications, the HIP4084 makes bridge based designs simple and flexible. With operation up to 80V and undervoltage detection, the device is best suited to applications of moderate power levels. Like the HIP4081, the HIP4084 has a flexible input protocol for driving every possible switch combination. Like the HIP4082, the HIP4084 provides a typical drive currents of 0.5A and a programmable dead time from 0.25s to 4.5s. Like the HIP4086, the HIP4084 allows override of shootthrough protection for switched reluctance applications. The HIP4084 is suitable for applications requiring DC to 100kHz. Unlike other HIP4080 family products, the HIP4084 provides, from a single pin, a programmable undervoltage set point and an enable/disable function. Ordering Information PART NUMBER HIP4084AB HIP4084AP TEMP. RANGE ( oC) -40 to 105 -40 to 105 PACKAGE 28 Ld SOIC 28 Ld PDIP PKG. NO. M28.3 E28.6 Applications * Brushless Motors * AC Motor Drives * Stepper Motors * Switched Reluctance Motor Drives For additional information contact Ivars Lauzums at (407) 729-5531. Pinout HIP4084 (PDIP, SOIC) TOP VIEW AHO 1 AHB AHI ALI BHI BLI VSS UVLO/EN 2 3 4 5 6 7 28 AHS 27 BHB 26 BHO 25 BHS 24 ALO 23 BLO 22 VDD 21 CLO 20 DLO 19 CHS 18 CHO 17 CHB 16 DHS 15 DHO Application Block Diagram 80V 12V HIP4084 RDEL 8 9 CHI 10 CLI 11 DHI 12 DLI 13 DHB 14 GND GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1 File Number 4222.1 HIP4084 TRUTH TABLE INPUT ALI, BLI, CLI, DLI X 1 0 0 1 AHI, BHI, CHI, DHI X X 0 1 0 UVLO/EN 0 1 1 1 1 RDEL X >100mV X X <100mV ALO, BLO, CLO, DLO 0 1 0 0 1 OUTPUT AHO, BHO, CHO, DHO 0 0 1 0 1 NOTE: X signifies that input can be either a "1" or "0". Pin Descriptions PIN NUMBER 2 27 17 14 3 5 10 12 SYMBOL AHB BHB CHB DHB (xHB) AHI BHI CHI DHI (xHI) DESCRIPTION High-side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin. High-Side Logic Level Inputs. Logic at these three pins controls the three high-side output drivers, AHO (Pin 1), BHO (Pin 26) and CHO (Pin 18) and DHO (Pin 15). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 8) to ground, the low side input of each phase will override the corresponding high side input on that phase. If RDEL is tied to ground, dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. EN (Pin 9) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold each xHI high if the pins are not driven. Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output drivers ALO (Pin 24), BLO (Pin 23) and CLO (Pin 21) and DLO (Pin 20). If the upper inputs are grounded then the lower inputs controls both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 8). EN (Pin 9) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than V DD). An internal 100A pull-up to V DD will hold xLI high if these pins are not driven. Ground. Connect the sources of the low-side power MOSFETs to this pin. Dead Time Setting. Connect resistor from this pin to V DD to set timing current that defines the dead time between drivers. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. When R DEL is tied to VSS, both upper and lowers can be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1F or smaller may be connected between R DEL and VSS. A resistor can be connected between this pin and V SS to program the under voltage set point. With this pin not connected the undervoltage setpoint is typically 6.6V. When this pin is tied to VDD, the undervoltage setpoint is typically 6.2V. With this pin tied to VSS, all six outputs are taken low, overriding all other inputs. High-Side Outputs. Connect the gates of the high-side power MOSFETs to these pins. 4 6 11 13 7 8 ALI BLI CLI DLI (xLI) VSS RDEL 9 RUV/EN 1 26 18 15 28 25 19 16 22 24 23 21 20 AHO BHO CHO DHO (xHO) AHS BHS CHS DHS (xHS) VDD ALO BLO CLO DLO (xLO) High-Side Source connection. Connect the sources of the high-side power MOSFETs to these pins. The negative side of the bootstrap capacitors should also be connected to these pins. Positive supply. De-couple this pin to VSS (Pin 7). Low-Side Outputs. Connect the gates of the low-side power MOSFETs to these pins. NOTE: x = A, B, C and D 2 HIP4084 Absolute Maximum Ratings TA = 25oC Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on xHS. . . . . . . . .-6V (Transient) to +85V (-40oC to 150oC) Voltage on xHB. . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to V DD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHB +0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) JA (oC/W) Operating Conditions Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V to +15V Voltage on V xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V Voltage on xHB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VxHS + VDD Operating Ambient Temperature Range . . . . . . . . . . -40oC to 105oC Operating Junction Temperature Range . . . . . . . . .-40oC to 105oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to VSS unless otherwise specified. 3. x = A, B, C, and D. For example, xHS refers to AHS, BHS, CHS, and DHS. Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, UVLO/EN = , Gate Capacitance (CGATE) = 1000pF TJ = 25oC TJ = -40oC TO 150oC MAX MIN MAX UNITS PARAMETER TEST CONDITIONS MIN TYP SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current VDD Operating Current xHB On Quiescent Current xHB Off Quiescent Current xHB Operating Current QPUMP Output Voltage QPUMP Output Current xHB, xHS Leakage Current VDD Rising Undervoltage Threshold VDD Falling Undervoltage Threshold Minimum Undervoltage Threshold xHI = 5V, xLI = 5V f = 20kHz, 50% Duty Cycle xHI = 0V xHI = VDD f = 20kHz, 50% Duty Cycle No Load VxHB = 10V VxHS = 80V, VxHB = 93V RUV Open RUV Open RUV = VDD 3 8 0.6 0.7 11.5 7 6.2 5.75 5 4 9.5 40 0.8 0.9 12.5 100 24 7.1 6.6 6.2 5 12 80 1.3 1.3 14 130 45 8.0 7.5 6.8 10.5 6.1 5.6 4.9 2 7 0.5 6 13 100 1.4 2.0 14.5 140 50 8.1 7.6 6.9 mA mA A mA mA V A A V V V INPUT PINS: ALI, BLI, CLI, DLI, AHI, BHI, CHI, DHI, AND EN Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current VIN = 0V VIN = 5V 2.5 60 -1 35 100 1.0 135 1 2.7 55 -10 0.8 140 10 V V mV A A GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, DLO, AHO, BHO, CHO, AND DHO Low Level Output Voltage (VOUT-VSS) Peak Pulse Pullup Current ISINKING = 30mA VOUT 0V to 5V 0.3 100 0.5 0.7 200 1.0 mV A 3 HIP4084 Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, UVLO/EN = , Gate Capacitance (CGATE) = 1000pF TJ = 25oC PARAMETER Peak Pulse Pulldown Current TEST CONDITIONS VOUT 12V to 4V MIN 0.7 TYP 1.1 MAX 1.5 TJ = -40oC TO 150oC MIN 0.5 MAX 1.7 UNITS A Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 10K, Gate Capacitance (CGATE) = 1000pF TJ = 25oC PARAMETER TURN ON DELAY AND PROPAGATION DELAY Dead Time RDEL = 100K RDEL = 10K Dead Time Channel Matching Lower Turn-Off Propagation Delay (xLI-xLO) Upper Turn-Off Propagation Delay (xHI-xHO) Lower Turn-On Propagation Delay (xLI-xLO) Upper Turn-On Propagation Delay (xHI-xHO) Rise Time Fall Time Turn-On Input Pulse Width Turn-Off Input Pulse Width Disable (EN) Turn-Off Propagation Delay (EN - xLO) Disable (EN) Turn-Off Propagation Delay (EN - xHO) Enable to Lower Turn-On Propagation Delay (EN - xLO) Enable to Upper Turn-On Propagation Delay (EN- xHO) Refresh Pulse Width (xLO) RDEL = 10K RDEL = 10K No Load 3.8 0.38 4.5 0.5 7 25 6 0.65 15 50 3 0.3 7 0.7 20 70 s s % ns TEST CONDITIONS MIN TYP MAX TJ = -40oC TO 150oC MIN MAX UNITS No Load - 55 80 - 100 ns No Load - 40 85 - 100 ns No Load - 75 110 - 150 ns CGATE = 1000pF CGATE = 1000pF 50 50 - 20 10 50 40 20 80 50 50 50 25 90 ns ns ns ns ns - 75 100 - 125 ns - 50 80 - 100 ns - 1.2 2 - 3 s s 375 580 900 350 950 4 HIP4084 Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 e eA eC C C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.600 BSC 0.115 28 0.700 0.200 - 2.54 BSC 15.24 BSC 17.78 5.08 28 2.93 5 HIP4084 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 8o 0o 8o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 A1 B C D E e H C e B 0.25(0.010) M C A M BS A1 0.10(0.004) 0.05 BSC 1.27 BSC h L N NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 6 |
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